The present invention relates to generating reference pulse trains and, more specifically, to being able to control shifting outputs of a multi-output phase locked loop (PLL) via an external control.
A phase-locked loop or phase lock loop (PLL) is a control system that generates a signal that has a fixed relation to the phase of a “reference” signal. A phase-locked loop circuit responds to both the frequency and the phase of the input signals, automatically raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase. A phase-locked loop is an example of a control system using negative feedback.
In a typical PLL, a phase detector compares two input signals and produces an error signal that is proportional to their phase difference. The error signal is then low-pass filtered and used to drive a voltage-controlled oscillator (VCO) that creates an output signal having an output frequency. The output signal is fed through a frequency divider back to the input of the system, producing a negative feedback loop. If the output frequency drifts, the error signal will increase, driving the VCO frequency in the opposite direction so as to reduce the error. Thus, the output is locked to the frequency at the other input. This input is called the reference input and is often derived from a crystal oscillator, which is very stable in frequency.
A frequency (or clock) divider is an electronic circuit that takes an input signal with an input frequency and generates an output signal with a frequency that is a fraction of the input frequency. PLLs make use of frequency dividers to generate multiple outputs having frequencies that are multiples of the input frequency.